1. Field of the Invention
This invention relates to processes of manufacture of integrated circuit chips and more particularly to production control of a manufacturing process therefor.
2. Description of Related Art
As currently practiced, shift performance indicators, which are monitored by shop personnel of integrated circuit (IC) fabrication lines, are time-lag performance indicators. There are three disadvantages of time-lag performance indicators. First, no timely production line information can be provided. Second, time-lag performance indicators are unfair to each shift because of interaction between shifts brought by time-lag performance indicators. Last, utilization of machine capacity is likely to drop during the period of shift transition, where the shift transition is defined as the transition of one shift going to be off duty and another shift going to be on duty.
U.S. Pat. No. 5,219,765 of Yoshida et al "Method for Manufacturing a Semiconductor Device Including Wafer Aging, Probe Inspection, and Feeding Back the Results of the Inspection to the Device Fabrication Process" describes a method for manufacturing semiconductor devices including test from which information is fed back for fabrication process improvement.
U.S. Pat. No. 5,240,866 of Friedman et al "Method for Characterizing Failed Circuits on Semiconductor Wafers" shows a method for characterizing failed circuits on semiconductor wafers.
U.S. Pat. No. 5,210,041 of Kobayashi et al "Process for Manufacturing Semiconductor Integrated Circuit Device" shows computer control of testing/feedback to chip manufacturing process.